This invention relates to a data processing technique, and particularly to a technique which may be effectively applied to a micro computer system, for example, a micro processor of a microprogram control system.
A control system in a micro processor includes a microprogram control system in which the controls of a data transfer sequence and of an operation sequence for an execution unit comprising an adder and registers are carried out in accordance with a microprogram stored in a read only memory (a control storage unit, referred to as micro ROM hereinafter).
When a register in an execution unit is specified in a micro processor of such a microprogram control system, there is a system, as shown in FIG. 5, in which either machine language instruction code B introduced in an instruction register IR or a micro instruction code C read from a micro ROM, .mu.-ROM, is selected by a selector SEL and is then provided for an address decoder AD so that the selected micro instruction code is decoded by the address decoder and the specification signals D.sub.1, D.sub.2, . . . D.sub.n of the register are produced.
In the above-described system, the selection of the machine instruction code or the micro instruction code in the selector SEL is performed by switch signals S output from the decoder DEC (not shown in the figure) which receives part of the micro instruction code read from the micro ROM, .mu.-ROM.
An invention with respect to the system in which, as described above, the content either of the micro ROM for carrying out control storage or the register is selected by the selector and then provided for the decoder so as to produce control signals such as register specification signals is described, for example, in Japanese Patent Publication No. 25251/1984.
However, the above-described system for the production of control signals has the disadvantage that the operation speed is slow, as described below. Namely, the switch signals S are produced by providing the decoder DEC with the output A of the micro ROM, .mu.-ROM, as shown in FIG. 6-B, and either the micro instruction code C or the machine language instruction code B is selectively provided for the address decoder AD on the basis of the switch signals S, resulting in the production of the specification signals D.sub.1, D.sub.2, . . . for specifying the register, etc. That is to say, the decoding in the decoders DEC and AD is conducted in time series. Consequently, it has been found by the inventors of this invention that the above system involved the disadvantage that the production of the specification signals D.sub.1, D.sub.2, . . . is delayed by a total time equivalent to the sum of the individual decoding time of each of the decoders and the operation, speed is thus very slow.